View AX88655P_4610201.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

asix electronics corporation first released date: 01/31/2002 4 f, no. 8 , hsin ann rd. , science - based industrial park, hsin - chu city, taiwa n, r.o.c. tel: 886 - 3 - 579 - 9500 fax: 886 - 3 - 563 - 9 799 http://www.asix.com.tw ax8865 5 p 5 - port 10/100/1000base - t ethernet switch 5 - port gigabit ethernet switch with embedded memory document no.: ax88655 - 1.0 / v1.0 / mar, 12,2002 features 5 - port gigabit ethernet switch integrating macs, packet buffer memory and switching engine with gmii /mii interface full duplex 1000 mbit/s. full and half duplex 10/100 mbit/s supports auto - sensing or manual selection for speed and duplex capability with an embedded mpu store - and - forward operation support performs full wire - speed switching with no hol blocking broadcast storm control quality - of - serv ice provisioning on 802.1p tag and port - pairs with two priority queues embedded 128k byte sram for packet buffer integrated two - way address - lookup engine and table for 4k mac addresses programmable aging mechanism for the two - way 4k mac addresses table ful l - duplex ieee 802.3x flow control half - duplex back pressure flow control port trunking for high - bandwidth links provides 5 gpio ports provides eeprom interface for auto - configuration system clock input is one 2 7 mhz crystal and one 125mhz oscillator 2.5 and 3.3v operations 3.3 i/os and packaged in 256 - pin pqfp product description the ax88655 is a 5 - port 10/100/1000 mbps ethernet switch with gmii or mii interface. the switch controller provides network system manufacturers the ideal platform for building smart and cost - effective backbone switches for small to medium sized businesses. the ax88655 5 - port 10/100/100 base - t single chip switch controllers combine the benefits of network simplicity, flexibility and high integration. its highly integrated feat ure set enables network system manufacturers to build smart switches for the fast - growing small to medium business market segment. benefits of ax88655 switches are below. ? simplicity provides a smart, simple and low maintenance plug - and - play network inter connect system for small to medium size businesses ? flexibility highly scalable configuration allows system manufacturers to enable or disable a range of features to best meet their target price point ? integration highly integrated design drives down overa ll switch manufacturing costs. target applications 5 - port gigabit layer 2 switches for workgroup high - port count layer 2 switches with trunking high performance solution of ethernet backbone always contact asix for possible updates before starting a d esign. this data sheet contains new products information. asix electronics reserves the rights to modify the product specification without notice. no liability is assumed as a result of the use of this product. no rights under any patent accompany the sale of the product.
asix electronics corporation 2 ax886 55 p 5 - port 10/100/1000base - t ethernet switch system block diagram ax88655 p switch controller eeprom 5 * 10/100/1000 mbps phys
asix electronics corporation 3 ax886 55 p 5 - port 10/100/1000base - t ethernet switch contents 1.0 ax88655 overview ................................ ................................ ................................ ............. 6 1.1 g eneral d escription ................................ ................................ ................................ ..................... 6 1.2 ax88655 b lock d iagram ................................ ................................ ................................ . 6 1.3 p in c onnection d iagram ................................ ................................ ................................ ............. 7 2.0 i/o definition ................................ ................................ ................................ ................................ ............... 8 2.1 gmii/mii i nterface ................................ ................................ ................................ ........................ 8 2.1.1 gmii interface port 0 ................................ ................................ ................................ ................................ 8 2.1.2 gmii interface port 1 ................................ ................................ ................................ ................................ 9 2.1.3 gmii interface port 2 ................................ ................................ ................................ ................................ 9 2.1.4 gmii interface port 3 ................................ ................................ ................................ ................................ 9 2.1.5 gmii interface port 4 ................................ ................................ ................................ .............................. 10 2.2 m iscellaneous ................................ ................................ ................................ ................................ . 10 3.0 functional descr iption ................................ ................................ ................... 12 3.1 i ntroduction ................................ ................................ ................................ ................................ ..... 12 3.2 p acket f iltering and f orwarding p rocess ................................ ................................ . 12 3.3 mac a ddress r outing , l earning and a ging p rocess ................................ .......... 12 3.4 f ull d uplex 802.3 x f low c ontrol ................................ ................................ ..................... 12 3.5 h alf d uplex b ack p ressure c ontrol ................................ ................................ .............. 12 3.6 mii p olling ................................ ................................ ................................ ................................ ......... 12 3.7 p ort - b ased q o s: p ort - p air ................................ ................................ ................................ ... 13 4.0 register descrip tions ................................ ................................ ......................... 14 4.1 r egister 00 ................................ ................................ ................................ ................................ .................... 14 4.2 r egister 01 ................................ ................................ ................................ ................................ .................... 14 4.3 r egister 02 ................................ ................................ ................................ ................................ .................... 14 4.4 r egister 03 ................................ ................................ ................................ ................................ .................... 15 4.5 r egister 04 ................................ ................................ ................................ ................................ .................... 15 4.6 r egister 05 ................................ ................................ ................................ ................................ .................... 15 4.7 r egister 06 ................................ ................................ ................................ ................................ .................... 15 4.8 r egister 07 ................................ ................................ ................................ ................................ .................... 15 4.9 r egister 08 ................................ ................................ ................................ ................................ .................... 15 4.10 r egister 09 ................................ ................................ ................................ ................................ .................. 15 4 .11 r egister 0a ................................ ................................ ................................ ................................ ................. 15 4.12 r egister 0b ................................ ................................ ................................ ................................ ................. 16 4.13 r egister 0c ................................ ................................ ................................ ................................ ................. 16 4.14 r egister 0d ................................ ................................ ................................ ................................ ................. 16 4.15 r egister 0e ................................ ................................ ................................ ................................ ................. 16 4.16 r egister 0f ................................ ................................ ................................ ................................ .................. 17 4.17 r egister 10 ................................ ................................ ................................ ................................ .................. 17 4.18 r egister 11 ................................ ................................ ................................ ................................ .................. 18 4.19 r egister 12 ................................ ................................ ................................ ................................ .................. 18 4.20 r egister 13 ................................ ................................ ................................ ................................ .................. 18 4.21 r egister 14 ................................ ................................ ................................ ................................ .................. 18
asix electronics corporation 4 ax886 55 p 5 - port 10/100/1000base - t ethernet switch 5.0 electrical speci fication and timing ................................ ..... 19 5.1 a bsolute m aximum r atings ................................ ................................ ................................ ... 19 5.2 g eneral o peration c onditions ................................ ................................ ............................ 19 5.3 dc c haracteristics ................................ ................................ ................................ ..................... 19 5.4 ac specifications ................................ ................................ ................................ ........................... 20 5.4.1 x_in signal timing ................................ ................................ ................................ ................................ .. 20 5.4.2 reset signal timing ................................ ................................ ................................ ................................ . 20 5.4.3 gmii transmi t/receive signals timing ................................ ................................ ................................ .... 21 5.4.4 100 mbps mii transmit/receive signals timing ................................ ................................ ...................... 22 5.4.5 10 mbps mii transmit/receive signals timing ................................ ................................ ........................ 23 6.0 package informat ion ................................ ................................ .......................... 25 appendix a: system a pplications ................................ ............................... 26 a.1 ax88655 as 5 - p ort soho high traffic power u ser switch ................................ ................................ ...... 26 a.2 ax88655 as 5 - p ort s mart switch (dip switch configurable ) ................................ ................................ . 26 a.3 ax88655 for 10/100m bps e thernet b ackbone ................................ ................................ .......................... 27 a.4 ax88655 for s uper s erver t runking a pplication ................................ ................................ .................... 27 appendix b: design n ote ................................ ................................ .............................. 28 b.1 u sing mii i/f connects to mac ................................ ................................ ................................ .................. 28 appendix c: weight s etting for qos ................................ ..................... 29 demonstration circui t (a) : ax8865 8 smart switch ... 30
asix electronics corporation 5 ax886 55 p 5 - port 10/100/1000base - t ethernet switch figures f ig - 1 ax88655 b lock d iagram ................................ ................................ ................................ ........... 6 f ig - 2 ax88655 p in d iagram ................................ ................................ ................................ ................... 7
asix electronics corporation 6 ax886 55 p 5 - port 10/100/1000base - t ethernet switch 1.0 ax88655 overview 1.1 general description the ax88655 gigabit switch controller supports five 10/100/1000 mbps ports in wire - speed operation. the ax88655 gigabit switch controller provides five 10/100/1000 ethernet ports with gmii/mii interface. for each ports, the ax88655 supports gmii (802.3ab) interface with full - duplex operation at gigabit speed, full - or half - duplex operation at 10/100 mbps speed and polls the status of phys with an embedded mpu. embedded 128k bytes sram as a packet buffer operates with an internal 90 mhz clock. for efficient utilization of the packet buffer, there are 1024 128 - byte page - links totally in the buffer. the device supports 4k internal mac addresses which are shared by all ports with an embedded 32k byte ssram. the learning/routing engine is implemented with a two - way hash/linear algorithm to reduce possibility of routing collision. basically the ax88655 supports non - blocking wire speed forwarding rate and no head - of - line (hol) blocking issue. the ax88655 provi des two flow - control mechanisms to avoid loss of data: an optional jamming based backpressure flow control in the half - duplex operation and ieee 802.3x in the full - duplex mode. to support quality of service (qos), each output port has two priority queues and their assignment can be based on the 802.1p priority field or port - pair setting. each output port retrieves the frames from the shared buffer based on queuing and sends them to the transmitting (tx) fifo. 1.2 ax88655 block diagram fig - 1 ax88655 block diagram 10/100/1000 mac 10/100/1000 mac 10/100/1000 mac high speed switch fabric routing /learning engine buffer manager packe t buffer general purpose i/o interface (gpio) gmii phy address look - up table 10/100/1000 mac 10/100/1000 mac eeprom interface gmii phy gmii phy gmii phy gmii phy gpio configuration logic
asix electronics corporation 7 ax886 55 p 5 - port 10/100/1000base - t ethernet switch 1.3 pin connection diagram fig - 2 ax88655 pin diagram 135 gpio2 35 65 100 180 tx_en0 92 94 104 253 rx_dv4 avdd25d nc 224 235 rxd0[1] nc nc 255 237 /rst tx_clk1 rx_dv1 gtx_clk4 nc nc 1 12 205 176 col0 vdd25 96 197 vss txd2[5] nc 109 txd1[1] gpio3 nc 20 107 167 rxd0[3] sid4 76 148 vdd25 nc 215 rxd0[6] txd1[2] 19 62 111 vss vdd25 vss rxd2[5] nc 7 72 196 158 rxd3[7] col4 191 nc 105 118 212 10/100/1000mbps rxd4[7] 36 45 150 169 rxd1[6] col2 vss txd4[0] nc nc 240 /gclk_en 51 43 139 col1 vss25 avdd25a nc 10 11 54 86 186 161 rxd4[5] txd2[4] 182 txd3[0] nc 152 219 226 txd0[3] 66 rxd3[5] txd3[3] vss nc 127 txd0[4] 83 130 vss sid0 29 31 57 138 122 rxd1[4] sid2 15 101 190 171 250 txd2[0] txd2[6] gclk nc 172 rxd0[7] rxd4[4] txd4[6] nc 223 nc 39 81 vss vss 192 248 rxd3[1] vss25 nc 21 60 69 143 113 vdd25 77 154 181 241 col3 vss vss vss nc vss25 rxd2[6] 2 23 236 vdd25 tx_en4 avss25d 64 97 238 vss rx_dv3 rxd1[2] nc 178 157 vss nc 132 rxd1[1] txd3[7] 27 112 202 vdd25 88 175 tx_en3 204 rx_dv2 47 mdc rxd2[3] vss nc 14 68 155 140 rxd0[5] txd1[3] gtx_clk1 nc 73 108 185 162 252 sdc rxd2[7] nc 230 rx_clk1 rxd4[0] rx_clk2 gpio4 filter nc 34 218 213 225 91 rxd4[3] vss vss 133 123 208 rx_clk4 txd4[7] gpio0 5 16 136 115 124 rxd0[4] vss nc 95 102 188 173 254 246 vdd25 nc 52 txd2[1] nc vss 40 222 211 rx_dv0 gtx_clk3 vss txd4[1] nc nc nc 48 142 128 txd0[6] vdd33 vss rxd2[0] vss nc 8 78 110 251 rxd1[7] x_in 3 153 170 168 245 rxd4[6] vdd25 24 58 nc 55 98 233 229 rx_clk0 rxd0[0] 79 90 txd0[1] tx_en1 rxd4[2] nc 53 nc 114 199 rxd3[6] txd3[2] rxd1[5] rxd2[4] 13 84 116 txd0[5] 156 tx_en2 sysclk vss nc nc 33 46 nc 61 106 198 crs2 74 164 txd1[5] rxd3[3] vss nc nc 184 179 160 243 vss vdd33 193 switch controller txd2[7] 30 70 239 210 txd3[5] vss crs3 rxd3[0] sid1 vss 6 147 134 207 vss vdd25 nc 82 137 256 rxd3[4] /sysclk_en 26 189 177 249 vdd25 avss25a 41 ethernet txd3[4] rxd2[1] nc 85 221 228 tx_clk4 gpio1 nc 93 217 tx_clk0 vss vss nc 17 49 125 txd4[4] vss 63 117 129 201 nc 87 247 rxd1[3] crs1 txd4[5] vss 166 165 242 rx_clk3 nc 50 67 99 103 vdd25 x_out 89 214 txd2[2] nc nc 231 txd1[4] mdio 38 txd1[6] rxd4[1] 203 194 vdd25 crs0 nc 9 vdd25 vdd25 tx_clk2 44 121 txd4[3] nc nc 22 145 149 gtx_clk2 75 144 232 txd2[3] nc 163 rxd3[2] 18 56 120 183 174 159 rxd0[2] txd0[0] 71 195 txd0[2] sid3 vss 4 AX88655P tx_clk3 txd3[1] vdd25 59 209 txd0[7] vdd25 vss 25 151 200 119 206 234 crs4 141 244 avbb25 nc 32 42 187 nc 28 80 nc 146 220 227 txd1[7] sdio 216 rxd1[0] txd1[1] txd3[6] vdd25 vss vss 37 126 gtx_clk0 131 txd4[2] rxd2[2] nc
asix electronics corporation 8 ax886 55 p 5 - port 10/100/1000base - t ethernet switch 2.0 pin descriptions 2.0 i/o de finition the following terms describe the ax88655 pin - out: all pin names with the ?/? suffix are asserted low. the following abbreviations are used in following tables . i input pu pull up o output pd pull down i/o input/output p power pin od open dr ain 2.1 gmii/mii interface 2.1.1 gmii interface port 0 signal name i/o pin no. description gtx_clk0 o 250 125mhz clock output: it is a continuous 125 mhz clock output to giga - phy operating at 1000base - t. that is, it is a timing reference for tx_en0 and txd0[7:0] tx_en0 o 5 transmit enable: when tx_en0 is asserted, data on txd0[7:0] are transmitted onto phy. tx_en0 is synchronous to gtx_clk0 in 1000base - t mode and synchronous to tx_clk0 in 10/100base - t mode. txd0[7:0] o 4 ? 1, 256 ? 253 transm it data: synchronous to the rising of gtx_clk0 in 1000base - t mode. and synchronous to rising edge of tx_clk0 in 10/100base - t mode. tx_clk0 i/pd 252 mii transmit clock input: tx_en0 and txd0[3:0] are synchronous to the rising edge of this clock in 10/100ba se - t mode. col0 i/pd 238 collision detect: active high to indicate that there is collision occurred in half duplex mode. in full duplex mode col0 is always low. crs0 i/pd 237 carrier sense: active high if there is carrier on medium. in half duplex mode crs0 is also asserted during transmission and asynchronous to any clock. rx_dv0 i 248 receive data valid: active high to indicate that data presented on rxd0[7:0] is valid and synchronous to rx_clk0. rx_clk0 i 247 receive clock input: 125, 25 and 2.5 mhz is running at 1000/100/10 base - t mode respectively. rx_dv0 and rxd0[7:0] are synchronous to rising edge of this clock. rxd0[7:0] i/pd 246 - 239 receive data: data received by the phy are presented on rxd0 and synchronous to rx_clk0. rxd0[3:0] is vali d in 10/100 /1000 base - t and rxd[ 7:4 ] is valid only in 1 00 0base - t modes.
asix electronics corporation 9 ax886 55 p 5 - port 10/100/1000base - t ethernet switch 2.1.2 gmii interface port 1 signal name i/o pin no. description gtx_clk 1 o 57 125mhz clock output: please references section 2.1.1. tx_en 1 o 68 transmit enable: please referenc es section 2.1.1. txd 1 [7:0] o 67 ? 60 transmit data: please references section 2.1.1. tx_clk 1 i/pd 59 mii transmit clock input: please references section 2.1.1. col 1 i/pd 45 collision detect: please references section 2.1.1. crs 1 i/pd 44 carrier sens e: please references section 2.1.1. rx_dv 1 i 55 receive data valid: please references section 2.1.1. rx_clk 1 i 54 receive clock input: please references section 2.1.1. rxd 1 [7:0] i/pd 53 - 46 receive data: please references section 2.1.1. 2.1.3 gmii interface port 2 signal name i/o pin no. description gtx_clk 2 o 84 125mhz clock output: please references section 2.1.1. tx_en 2 o 95 transmit enable: please references section 2.1.1. txd 2 [7:0] o 94 ? 87 transmit data: please references section 2.1. 1. tx_clk 2 i/pd 86 mii transmit clock input: please references section 2.1.1. col 2 i/pd 72 collision detect: please references section 2.1.1. crs 2 i/pd 71 carrier sense: please references section 2.1.1. rx_dv 2 i 82 receive data valid: please references section 2.1.1. rx_clk 2 i 81 receive clock input: please references section 2.1.1. rxd 2 [7:0] i/pd 80 - 73 receive data: please references section 2.1.1. 2.1.4 gmii interface port 3 signal name i/o pin no. description gtx_clk 3 o 111 125mhz clock ou tput: please references section 2.1.1. tx_en 3 o 122 transmit enable: please references section 2.1.1. txd 3 [7:0] o 121 ? 114 transmit data: please references section 2.1.1. tx_clk 3 i/pd 113 mii transmit clock input: please references section 2.1.1. col 3 i/pd 99 collision detect: please references section 2.1.1. crs 3 i/pd 98 carrier sense: please references section 2.1.1. rx_dv 3 i 109 receive data valid: please references section 2.1.1. rx_clk 3 i 108 receive clock input: please references section 2 .1.1. rxd 3 [7:0] i/pd 107 - 100 receive data: please references section 2.1.1.
asix electronics corporation 10 ax886 55 p 5 - port 10/100/1000base - t ethernet switch 2.1.5 gmii interface port 4 signal name i/o pin no. description gtx_clk 4 o 138 125mhz clock output: please references section 2.1.1. tx_en 4 o 149 transmit enable: plea se references section 2.1.1. txd 4 [7:0] o 148 ? 141 transmit data: please references section 2.1.1. tx_clk 4 i/pd 140 mii transmit clock input: please references section 2.1.1. col 4 i/pd 126 collision detect: please references section 2.1.1. crs 4 i/pd 125 carrier sense: please references section 2.1.1. rx_dv 4 i 136 receive data valid: please references section 2.1.1. rx_clk 4 i 135 receive clock input: please references section 2.1.1. rxd 4 [7:0] i/pd 134 - 127 receive data: please references section 2 .1.1. 2. 2 miscellaneous signal name i/o pin no. description x_in i 35 crystal or osc 27 mhz input: this is a clock source of pll. the pll will generate a 90 mhz internal clock . x_o ut o 36 crystal 2 7 mhz output: this pin should be floating with single - en ded external clock. gclk i 1 61 osc 125mhz input: 125mhz clock for gmii sysclk i 168 system clock input: 85 ~ 90mhz clock for switch kernel /gclk _en i /pu 157 gclk enable: 0) use gclk; 1) reserved /sysclk_en i /pu 158 system clock enable: 0) use sysclk ; 1) 90mhz generated by int ernal pll circuit from x_in clock source. filter i 4 0 filter : for internal pll circuit use. /rst i 170 reset: active low mdio i/o / pu 165 station management data in/out: phy management data input and output. mdc o 166 station management data clock out: phy management clock. sdio i/o / pu 163 eeprom data in/out: eeprom serial data input and output. sdc i/ o / pu 164 eeprom data clock in/out: eeprom serial clock. (note: it is output pin if the embedded mpu is active; otherwise as input pin) sid[4:0] i/pd i/pd i/pd i/up i/up 156, 155, 154, 153, 152 switch id: mpu can identify the switch and phys with this id. default is ?00011b?. gpio[4:0] i/o /pu 180 - 176 general purpose i/o: the 5 gpios can be programmed for special application . (note: the function is not released to user normally. please contact with asix directly if any requirement)
asix electronics corporation 11 ax886 55 p 5 - port 10/100/1000base - t ethernet switch nc n/a 8, 9, 41, 15, 16, 17, 21, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 43, 167, 172, 173 , 174, 175, 183, 184, 189, 190, 191, 192, 196, 198, 19 9, 200, 201, 202, 203, 204, 205, 206, 207, 210, 211, 216, 217, 218, 219, 223, 225, 226, 227, 228, 229, 230, 231, 232, 233, 234 nc: no connect. vdd33 i 34, 171, 3.3v +/ - 5% supply voltage. vdd25 p 7, 22, 58, 70, 85, 97, 112, 124, 139, 151, 162, 182, 19 7, 209, 224, 236, 251 2.5v +/ - 5% supply voltage. vss p 6, 10, 11, 12, 13, 18, 19, 20, 33, 56, 69, 83,96, 110, 123, 137, 150, 157, 159, 160, 167, 169, 181, 185, 186, 187, 188, 193, 194, 195, 208, 212, 213, 214, 215, 220, 221, 222, 235, 249 ground avbb25 p 37 ground for pll avdd25a p 38 2.5v +/ - 5% supply voltage for pll. avss25a p 39 ground for pll avdd25d p 4 2 2.5v +/ - 5% supply voltage for pll. avss25d p 4 1 ground for pll
asix electronics corporation 12 ax886 55 p 5 - port 10/100/1000base - t ethernet switch 3.0 functional description 3.1 introduction in general, the ax88655 device is a highly integrated layer 2 switch. it supports five 10/100/1000 ports with on - chip macs. it also supports integrated switching logic, packet queuing memory and packet storage memory. the ax88655 is capable of routing - and - forwarding packets at wire spe ed on all ports regardless of packet size. it is a low cost solution for five ports gigabit ethernet backbone switch design. no cpu interface is required; after power on reset, ax88655 provide an auto load configuration setting function through a 2 wire s erial eeprom interface to access external eeprom device, and ax88655 can easily be configured to support trunking, qos, ieee 802.3x flow control threshold setting, broadcast storm control ...etc functions. an overview of ax88658?s major functional blocks is shown in fig - 1 . 3.2 packet filtering and forwarding process the switch use simple store - and - forward algorithm as packet switching method. after receives incoming packets, the packets will be stored to the embedded memory first. the ax88655 searches in the address - lookup table with da of the packet. the packet will be forward to its destination port, if this packet?s da hits; otherwise this packet will be broadcasted. of course, only good packets will be forward. conditions of good packets are below: 1. crc is correct. 2. 64 bytes < packetlength < 1518/1522 bytes 3. not local packets, that is, it is a local packets if its sourceport is its destinatio n port. 4. not pause or other control packets. 5. not the same trunking group. 3.3 mac address routing, learning and aging process the switch supports 4k mac entries for switching. two - way dynamic address learning is performed by each good unicast packet is completely received . a nd linear/xor hash algorithm of the static address learning is achieved by eeprom configuration. o n the other hand, the routing process is performed whenever the packet?s da is captured. if the da can not get a hit result, the packet is going to broadcast. only the learned address entries are scheduled in the aging machine. if one station does not tra nsmit any packet for a period of time, the belonging mac address will be kicked out from the address table. the aging out time can be program automatically through the eeprom configuration. (default value is 300 seconds) 3.4 full duplex 802.3x flow contr ol in full duplex mode, ax88655 supports the standard flow control mechanism defined in ieee 802.3x standard. it enables the stopping of remote node transmissions via a pause frame information interaction. when space of the packet buffer is less than the i nitialization setting threshold value, ax88655 will send out a pause - on packet with pause time equal to ? x fff? to stop the remote node transmission. and then ax88655 will send out a pause - off packet with pause time equal to zero to inform the remote node t o retransmit packet if has enough space to receive packets. 3.5 half duplex back pressure control in half duplex mode, ax88655 provide a backpressure control mechanism to avoid dropping packets during network conjection situation. when space of the packet buffer is less than the initialization setting threshold value, ax88655 will send a jam pattern in the input port when it senses an incoming packet, thus force a collision to make the remote node transmission back off and will effectively avoid dropping p ackets. and then ax88655 will not send out a jam packet any more if has enough space to receive one packet. 3.6 mii polling the ax88655 supports phy management through the serial mdio/mdc interface. that is, the ax88655 access related
asix electronics corporation 13 ax886 55 p 5 - port 10/100/1000base - t ethernet switch register of phys v ia mdio/mdc interface after power on reset. the ax88655 will periodically and continuously poll and update the link status and link partner?s ability which include speed, duplex mode, and 802.3x flow control capable status of the connected phy devices thro ugh mdio/mdc serial interface. 3. 7 port - based qos: port - pair ax88655 provides 4 port - pairs for bandwidth management. users can assign any two ports as one port - pair with internal registers basically. any packets will put the high priority queue of the po rt - pair when send the packets each other. that is, two ports of each port - pair will obtain more bandwidth than other ports when congestion. in addition, one port can be as the highest priority port if one all_bit of a port - pair is active. that is, user ca n assign format of the port - pair as oneport - to - all and every packets of the oneport will put in the high priority transmit queue of other ports.
asix electronics corporation 14 ax886 55 p 5 - port 10/100/1000base - t ethernet switch 4.0 register descriptions registers table summary: address 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 default 00 h reserved 0000 h 01 h reserved 0000 h 02 h reserved rxflowctrl[ 4 :0] reserved txflowctrl[ 4 :0] 0000 h 03 h reserved 00 00 h 04 h reserved 00 00 h 05 h reserved 0000 h 06 h reserved 00 00 h 07 h reserved 1215 h 08 h reserved 7777 h 09 h reserved 7777 h 0a h portpair1[7:0] portpair0[7:0] 0000 h 0b h portpair3[7:0] portpair2[7:0] 0000 h 0c h lowqueueweight[3:0] reserved lw_lowqueuediscardlimit [9:0] 1060 h 0d h highqueueweight[3:0] maxstorm lw_highqueuediscardlimit [9:0] 1060 h 0e h res . pto mpl res erved sr sp nsb reserved qos[1:0] ae hm res . 8880 h 0f h reserved maxage [8:0] 1865 h 10 h reserved trunk30[2:0] reserved 00c0 h 11 h reserved lowqueueflowctrlmark[9:0] 0010 h 12 h maxjam[5:0] highqueueflowctrlmark[9:0] 2810 h 13 h reserved hw_lowqueue discardlimit[9:0] 0070 h 14 h reserved hw_highqueuediscardlimit[9:0] 0070 h notes: 1. the word ? reserved ? = ? res. ? on the above table. notes: 2. care must be taken that the ? reserved ? registers should keep the default value always. change of any reserv ed value may be resulting in unpredictable conditions. notes: 3. the registers can be accessed by internal mpu only. the mpu will read in configuration table, located on eeprom at somewhere address, and programs the above registers when every time power on or after system reset. 4.1 register 00 bit r/w description 15:0 r/w reserved 4.2 register 01 bit r/w description 15:0 r/w reserved 4.3 register 02 bit r/w description 15:13 r/w reserved
asix electronics corporation 15 ax886 55 p 5 - port 10/100/1000base - t ethernet switch 12 :8 r/w flowctrlenable for mac?s receive part of port[4:0] are configured by internal 8051 0: not identify pause frames by receive part of mac 1: can identify pause frames. that is, pausetimer of mac will be active. 7:5 r/w reserved 4 :0 r/w flowctrlenable for mac?s transmit part of port[4:0] are con figured by internal 8051 0: not send pause frames or jam 1: send pause frames for full - duplex when the packet buffer is empty. send jam frames for half - duplex when the packet buffer is empty. 4.4 register 03 bit r/w description 15:0 r/w reserved 4.5 register 04 bit r/w description 15:0 r/w reserved 4.6 register 05 bit r/w description 15:0 r/w reserved 4.7 register 06 bit r/w description 15:0 r/w reserved 4.8 register 07 bit r/w description 15:0 r/w reserved 4.9 register 08 bi t r/w description 15:0 r/w reserved 4.10 register 09 bit r/w description 15:0 r/w reserved 4.11 register 0a bit r/w description 15 r/w all_bit of portpair #1 when qos[0] is high 14:12 r/w port_id of portpair #1 when qos[0] is high
asix electronics corporation 16 ax886 55 p 5 - port 10/100/1000base - t ethernet switch 11 r/w all_b it of portpair #1 when qos[0] is high 10:8 r/w port_id of portpair #1 when qos[0] is high 7 r/w all_bit of portpair #0 when qos[0] is high 6:4 r/w port_id of portpair #0 when qos[0] is high 3 r/w all_bit of portpair #0 when qos[0] is high 2:0 r/w port _id of portpair #0 when qos[0] is high 4.12 register 0b bit r/w description 15 r/w all_bit of portpair #3 when qos[0] is high 14:12 r/w port_id of portpair #3 when qos[0] is high 11 r/w all_bit of portpair #3 when qos[0] is high 10:8 r/w port_id of portpair #3 when qos[0] is high 7 r/w all_bit of portpair #2 when qos[0] is high 6:4 r/w port_id of portpair #2 when qos[0] is high 3 r/w all_bit of portpair #2 when qos[0] is high 2:0 r/w port_id of portpair #2 when qos[0] is high 4.13 register 0c bit r/w description 15:12 r/w weightforlowque : weight for low priority queues when qos is active (see appendix c) 11:10 r/w reserved 9:0 r/w lowwatermark of low priority queues when drop packets 4.14 register 0d bit r/w description 15:12 r/w weightf orhighque: weight for high priority queues when qos is active (see appendix c) 11:10 r/w maximum number of broadcast frames that can be accumulated in each input frame buffer. 00: disable broadcast storm control 01: 32 frames 10: 48 frames 11: 64 frames 9:0 r/w lowwatermark of high priority queues when drop packets 4.15 register 0e bit r/w description 15 r/w reserved 14 r/w 802.3x flow control frame recognition control 0: check for mac control frame da mac address in addition to the mac control type field 1: check only the mac control type field 13 r/w setting for maximum length of packet that received 0: 1518 byte 1: 1522 byte 12:11 r/w reserved 10 r/w software reset (only reset the switch kernel) 0: active 1: disable
asix electronics corporation 17 ax886 55 p 5 - port 10/100/1000base - t ethernet switch 9 r/w back - off algorithm s election 0: disable. device will perform the ieee standard exponential back off algorithm when a collision occurs. 1: enable. when collisions occur, the macs will back off up to 7 slots. 8 r/w 0: stop generate jam patterns after some collision that is de fined by maxjam[5:0] 1: never stop back - pressure 7 :5 r/w reserved 4:3 r/w qos selection 00: disable qos function 01: port - pair priority algorithm 10: 802.1p 2 r/w agingenable switch table entry aging control. only the dynamically learned addresses will be aged. all explicit entries will not age. the aging time is programmed in register 0f. 0: disable. the table aging process is disabled. 1: enable. the table aging process is enabled and a hardware process ages every dynamically learned table entry. 1 r/w hash algorithm selection 0: xor mapping 1: linear mapping 0 r/w reserved 4.16 register 0f bit r/w description 15:9 r/w reserved 8:0 r/w maxage. this is a seven - bit register containing unsigned integer for determining the address - aging timer. the resolution of the normal address aging is (64 m* maxage[8:0]) / freqencyofsystemclock. default value is 300 seconds. 4.17 register 10 bit r/w description 15:13 r/w reserved 12:10 r/w trunking selection for port[3:0] 000: disable trunking 001: disable trunking 010: one 2 - port trunking for port[ 1:0 ] 011: one 2 - port trunking for port[ 1:0 ] 100: one 2 - port trunking for port[ 3:2 ] 101: one 4 - port trunking 110: two 2 - port trunkings for port[3:2] and port[1:0] 111: one 4 - port trunking 9:0 r/w reserved
asix electronics corporation 18 ax886 55 p 5 - port 10/100/1000base - t ethernet switch 4.1 8 register 11 bit r/w description 15:10 r/w reserved 9:0 r/w low watermarkfor flowctrl. this is a ten - bit register containing unsigned integer for transmit queues whether generate pause - on or not. 4.19 register 12 bit r/w description 15:10 r/w maxjam . this is a six - bit register containing unsigned integer for determining the jam counter whether generate jam or not. 9:0 r/w high watermarkfor flowctrl. this is a ten - bit register containing unsigned integer for transmit queues whether generate pause - off o r not. 4.20 register 13 bit r/w description 15:10 r/w reserved 9:0 r/w highwatermark of low priority queues when drop packets 4.21 register 14 bit r/w description 15:10 r/w reserved 9:0 r/w highwatermark of high priority queues when drop packets
asix electronics corporation 19 ax886 55 p 5 - port 10/100/1000base - t ethernet switch 5.0 electrical specification and timing 5.1 absolute maximum ratings description sym min max units operating temperature ta 0 +70 c storage temperature ts - 55 +150 c supply voltage vcc - 0.3 +4.0 v input voltage vin - 0.3 vdd+0.5 v outpu t voltage vout - 0.3 vdd+0.5 v lead temperature (soldering 10 seconds maximum) tl - 55 +220 c note: stress above those listed under absolute maximum ratings may cause permanent damage to the device. exposure to absolute maximum ratings conditions for exte nded period, adversely affect device life and reliability 5.2 general operation conditions description sym min max units operating temperature ta 0 +70 c supply voltage vdd +3.0 +3.6 v 5.3 dc characteristics (vdd=3.0v to 3.6v, vss=0v, ta=0 c to 70 c) description sym min max units low input voltage vil vss - 0.3 0.8 v high input voltage vih 2 vdd+0.5 v low output voltage vol 0.4 v high output voltage voh 2.4 v input leakage current 1 (note 1) iil1 10 ua input leakage current 2 (note 2) iil1 500 ua output leakage current iol 10 ua description sym min tpy max units power consumption pc tbd ma note: 1. all the input pins without pull low or pull high. 2. those pins had been pull low or pull high.
asix electronics corporation 20 ax886 55 p 5 - port 10/100/1000base - t ethernet switch 5.4 ac specifications 5.4.1 x_in signal timing x _i n tr tf tlow symbol description min typ. max units t cyc cycle time 20 ns t high clk high time 8 10 12 ns t low clk low time 8 10 12 ns t r/ t f clk slew rate 1 - 4 ns 5.4.2 reset signal timing sysclk /rst symbol description min typ. max units trst reset pulse width 10 - - sysclk tcyc thigh
asix electronics corporation 21 ax886 55 p 5 - port 10/100/1000base - t ethernet switch 5.4.3 gmii transmit/receive signals timing t0 t1 gtx_clk t2 t3 tx_en txd [7:0] symbol description min typ. max units t0 gtx_clk clock cycle time 7.998 8 8.002 ns t1 gtx _clk clock high time 4 ns t2 tx_en and txd data setup to gtx_clk rising edge 2.5 ns t3 tx_en and txd data hold from gtx_clk rising edge 0.5 ns t4 t5 r x_clk t6 t 7 rx_dv rxd [7:0] symbol description min typ. max units t4 r x_clk clock cycle time 7.998 8 8.002 ns t5 r x_clk clock high time 4 ns t6 rx_dv and rxd data setup to r x_clk rising edge 2.5 ns t7 rx_dv and rxd data hold from r x_clk rising edge 0.5 ns
asix electronics corporation 22 ax886 55 p 5 - port 10/100/1000base - t ethernet switch 5.4.4 100 mbps mii transmit/receive signals timing t0 t1 tx_clk t2 t2 tx_en t3 t3 txd [3:0] symbol description min typ. max units t0 tx_clk cycle time 39.996 40 40.004 ns t1 tx_clk high time 14 20 26 ns t2 tx_clk rising edge to tx_en delay 7.440 21.760 ns t3 tx_clk rising ed ge to txd delay 3.410 13.320 ns t4 t5 rx_clk t6 t6 rx_crs rx_dv t 7 t7 rxd [3:0] symbol description min typ. max units t4 rx_clk clock cycle time 39.996 40 40.004 ns t5 rx_clk clock high time 14 20 26 ns t6 r x_clk rising edge to rx_dv and rx_crs delay 3.0 13.0 ns t7 r x_clk rising edge to rxd delay 3.0 13.0 ns
asix electronics corporation 23 ax886 55 p 5 - port 10/100/1000base - t ethernet switch 5.4.5 10 mbps mii transmit/receive signals timing t0 t1 tx_clk t2 t2 tx_en t3 t3 txd [3:0] symbol description min typ. max units t0 tx_clk cycle time 399 . 96 40 0 400 . 04 ns t1 tx_clk high time 14 20 26 ns t2 tx_clk rising edge to tx_e n delay 7.440 21.760 ns t3 tx_clk rising edge to txd delay 3.410 13.320 ns t4 t5 rx_clk t6 t6 rx_crs rx_dv t 7 t7 rxd [3:0] symbol description min typ. max units t4 rx_clk clock cycle time 399. 96 40 0 400. 04 ns t5 rx_clk clock high time 14 0 20 0 26 0 ns t6 r x_clk rising edge to rx_dv and rx_crs delay 3.0 13.0 ns t7 r x_clk rising edge to rxd delay 3.0 13.0 ns
asix electronics corporation 24 ax886 55 p 5 - port 10/100/1000base - t ethernet switch
asix electronics corporation 25 ax886 55 p 5 - port 10/100/1000base - t ethernet switch 6.0 package information b e d hd e he pin 1 a2 a1 l l1 q milimeter symbol min. nom max a1 0.25 a2 3.4 b 0.16 d 28.00 e 28.00 e 0.4 hd 30.6 he 30.6 l 0.45 0.75 l1 1.3 q 0 7
asix electronics corporation 26 ax886 55 p 5 - port 10/100/1000base - t ethernet switch appendix a: system applications a.1 ax88655 as 5 - port soho high traffic power user switch a.2 ax88655 as 5 - port smart switch (dip switch configurable) ax88655 p switch controller quad gmii phy or 4 gmii phys 1 gmii phy seeprom for save configuration i/o port for configuration from pc ax8865 5p switch controller eeprom 5 * 10/100/1000mbps phys configuration serial in via gpio leds or general serial output via gpio dip sw
asix electronics corporation 27 ax886 55 p 5 - port 10/100/1000base - t ethernet switch a.3 ax88655 for 10/100mbps ethernet backbone wan router using 2 gigabit ports up - link and trunking form a 12.8g non - blocking backbone a.4 ax88655 for super server trunking application ax88655 p switch controller 16*10/100mbps +2*1000m bps ethernet switch 16*10/100mbps +2*1000mbps ethernet switch 5 - port gigabit switch ax88655 p switch controller super server with 2 * gigabit ethernet cards trunking 5 - port gigabit switch
asix electronics corporation 28 ax886 55 p 5 - port 10/100/1000base - t ethernet switch appendix b: design note b.1 using mii i/f connects to mac using mii interface to connect to mac type device application for ax88655 is illustrated bellow. 10k gnd ax88655 / switch ax88195 / mac note: 1. the mac needs to run at full - duplex mode. 2. care must be taken that the receive side has enough setup and/or hold time 3. some kind of cpu with embedded mac can also refer to this example col0 tx_en0 tx_clk0 txd0[3:0] crs0 rx_dv0 rx_clk0 rxd0[3:0] col crs rx_dv rx_clk rxd[3:0] rx_er tx_en tx_clk txd[3:0] tx_er 25mhz clock
asix electronics corporation 29 ax886 55 p 5 - port 10/100/1000base - t ethernet switch appendix c : weight setting for qos service ratio ( high : l ow ) weightforhighque[3:0] w eightforlowque[3:0] 1 : 1 4 ? b 0100 4 ? b 0100 2 : 1 4 ? b 0100 4 ? b 0010 3 : 1 4 ? b 0110 4 ? b 0010 4 : 1 4 ? b 0100 4 ? b 0001 5 : 1 4 ? b 0101 4 ? b 0001 6 : 1 4 ? b 0110 4 ? b 0001 7 : 1 4 ? b 0111 4 ? b 0001 8 : 1 4 ? b 1000 4 ? b 0001 9 : 1 4 ? b 1001 4 ? b 0001 10 : 1 4 ? b 1010 4 ? b 0001 11 : 1 4 ? b 1011 4 ? b 0001 12 : 1 4 ? b 1100 4 ? b 0001 13 : 1 4 ? b 1101 4 ? b 0001 14 : 1 4 ? b 1110 4 ? b 0001 15 : 1 4 ? b 1111 4 ? b 0001
30 asix electronics ax8865 5 p 5 - port 10/100/1000base - t ethernet switch demonstration circuit (a) : ax88658 smart switch gsw_root.sch 1.0 ax88655 p 5-port 10/100/1000base-t ethernet switch --- root ckt. c 1 10 thursday, march 14, 2002 asix electronics corporation title size document number rev date: sheet of power_ckt power_ckt vdd33 vdd25 vdd18_1 gnd rst#_p12 rst#_p0 rst#_sw rst_ctl# vdd18_2 vdd25_2 rst#_p34 rom_ckt rom_ckt vdd33 gnd sdio sdc rst_ctl# osc_ckt osc_ckt 25m_p0 25m_p1 25m_p2 25m_p3 25m_p4 gclk sysclk vdd33 gnd gsw_ckt gsw_ckt crs0 col0 rxd0[0..7] rx_clk0 rx_dv0 gtx_clk0 tx_clk0 txd0[0..7] tx_en0 crs1 col1 rxd1[0..7] rx_clk1 rx_dv1 gtx_clk1 tx_clk1 txd1[0..7] tx_en1 crs3 col3 rxd3[0..7] rx_clk2 rx_clk3 rx_rv2 rx_rv3 gtx_clk2 gtx_clk3 tx_clk2 tx_clk3 txd2[0..7] txd3[0..7] tx_en2 tx_en3 txd4[0..7] tx_en4 rxd4[0..7] gtx_clk4 tx_clk4 rx_clk4 rx_rv4 col4 crs4 gclk sysclk reset# vdd33 vdd25_2 gnd rxd2[0..7] crs2 col2 sdc sdio mdio mdc port4 gphy4 crs col rxd[0..7] rx_clk rx_dv gtx_clk tx_clk txd[0..7] tx_en mdio mdc phy_rst# 25mhz vdd25 vdd18 gnd port0 gphy0 crs col rxd[0..7] rx_clk rx_dv gtx_clk tx_clk txd[0..7] tx_en mdio mdc phy_rst# 25mhz vdd25 vdd18 gnd port1 gphy1 crs col rxd[0..7] rx_clk rx_dv gtx_clk tx_clk txd[0..7] tx_en mdio mdc phy_rst# 25mhz vdd25 vdd18 gnd port2 gphy2 crs col rxd[0..7] rx_clk rx_dv gtx_clk tx_clk txd[0..7] tx_en mdio mdc phy_rst# 25mhz vdd25 vdd18 gnd port3 gphy3 crs col rxd[0..7] rx_clk rx_dv gtx_clk tx_clk txd[0..7] tx_en mdio mdc phy_rst# 25mhz vdd25 vdd18 gnd mdc rst#_p12 25m_p1 mdio 25m_p1 25m_p0 25m_p2 25m_p3 25m_p4 25m_p2 rst#_p12 mdio mdc gnd sysclk gclk vdd33 rst#_sw vdd18_2 vdd25 vdd25_2 vdd33 gnd rst#_p12 rst#_p0 rst#_sw vdd18_2 gnd vdd25 vdd33 vdd18_2 rst_ctl# vdd18_1 vdd18_2 mdio 25m_p4 rst#_p34 mdc vdd25_2 mdc mdio vdd25 rst#_p0 25m_p0 vdd18_1 sdc sdio gnd vdd33 rxd2[0..7] gtx_clk1 col2 tx_clk4 tx_clk1 col1 rxd4[0..7] rx_clk2 rx_dv2 gtx_clk2 txd1[0..7] rx_dv1 rxd1[0..7] crs1 rx_dv4 col4 tx_en1 crs4 tx_en4 rx_clk1 txd2[0..7] tx_en2 crs2 txd4[0..7] gtx_clk4 tx_clk2 rx_clk4 gtx_clk0 rxd0[0..7] crs0 txd0[0..7] col0 tx_clk0 rx_clk0 rx_dv0 gnd gnd gnd tx_en0 mdc mdio rst#_p34 vdd25 tx_en3 crs3 25m_p3 mdc rxd3[0..7] gnd gtx_clk3 col3 rst#_p34 txd3[0..7] rx_clk3 gnd vdd18_2 mdio vdd25 vdd25 tx_clk3 rx_dv3 ax88655 p 5-port 10/100/1000base-t ethernet switch application.
asix electronics corporation 31 ax886 55 p 5 - port 10/100/1000base - t ethernet switch gphy0.sch 1.0 ax88655 p 5-port 10/100/1000base-t ethernet switch --- port 0 g'phy ckt. c 2 10 thursday, march 14, 2002 asix electronics corporation title size document number rev date: sheet of col vdd_o gnd vdd_c gnd gnd vdd_o tx_en gnd vdd_o gnd vdd_c phyadd2 speed duplex phyadd1 gnd vdd_o speed1 vdd_o gnd an_en gnd gnd vdd_c vdd_o gnd vdd_c vdd_c gnd gnd phyadd3 phyadd0 rx_vdd25 gnd vdd_o phyadd4 gnd gnd vdd_c vdd_c gnd rx_vdd25 vdd_o gnd gnd vdd_o gnd vdd_o gnd gnd vdd_c gnd txd1 vdd_c txd3 gnd gnd txd5 vdd_o txd2 txd4 txd0 vdd_o gnd txd6 txd7 gnd mdia_p gnd mdid_p gnd gnd gnd gnd vdd_c mdid_n vdd_c gnd gnd vdd_c mdic_p vdd_c mdib_p gnd gnd gnd mdic_n vdd_c mdib_n mdia_n gnd gnd gnd 25m_in mdc gtx_clk vdd_o mdio vdd_o vdd_c gtx_clk tx_en mdio mdc reset# 25m_in vdd25 vdd18 txd[0..7] crs col rx_clk rx_dv tx_clk rxd[0..7] mdid_p mdid_n rx_vdd25 mdic_n mdic_p rx_vdd25 rx_vdd25 mdia_n mdia_p rx_vdd25 mdib_n mdib_p phyadd2 phyadd3 duplex vdd_o phyadd0 phyadd1 phyadd4 an_en speed1 speed speed1 speed vdd_o phyadd0 an_en duplex vdd_o gnd rxd[0..7] rxd1 rxd5 rxd4 rxd3 rxd6 rxd7 rxd2 rxd0 txd[0..7] tx_clk rx_clk gnd reset# vdd_o vdd25 vdd_c vdd18 rx_vdd25 gnd crs rx_dv mdi_d+ mdi_c- mdi_c+ mdi_a+ mdi_a- mdi_b- mdi_b+ mdi_d- mdi_a- mdi_b+ mdi_d- mdi_b- mdi_d+ mdi_c- mdi_c+ mdi_a+ gnd gnd gnd gnd gnd vdd_o vdd_o vdd_o c40 0.1uf r29 49.9 d2 led c44 0.1uf r7 4.7k c5 0.1uf r3 4.7k c26 1000pf d5 led c41 0.1uf c59 0.1uf c56 0.1uf r35 49.9 l2 f.b. r40 1.5k r27 75 c47 1000pf shield jack1 rj45_a 2 4 6 1 3 5 7 8 11 12 r10 4.7k c33 0.1uf c7 0.1uf c58 0.1uf c35 0.1uf c27 0.1uf r12 1k r34 49.9 c60 0.1uf + c42 100uf/16v + c18 100uf/16v d1 led c55 0.1uf c3 0.1uf r33 4.7k l1 f.b. c30 0.1uf tf1 24hst1041 24 23 22 21 20 19 18 17 16 15 14 13 1 2 3 4 5 6 7 8 9 10 11 12 mct1 mx1+ mx1- mct2 mx2+ mx2- mct3 mx3+ mx3- mct4 mx4+ mx4- tct1 td1+ td1- tct2 td2+ td2- tct3 td3+ td3- tct4 td4+ td4- r2 4.7k c28 1000pf c25 0.1uf r16 1k c29 0.1uf r21 10 u1 dp83865avh 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 non_ieee_strap reserved /interrupt io_vdd vss tx_tclk activity_led /speed_strap link10_led /speed1_strap link100_led /duplex_strap an_en_strap /link1000_led core_vdd vss phyaddr0_strap /duplex_led phyaddr1_strap io_vdd vss phyaddr2_strap phyaddr3_strap core_vdd vss io_vdd vss reserved tck core_vdd vss tms tdo io_vdd vss tdi /trst /reset vdd_sel_strap core_vdd vss io_vdd vss col crs rx_er io_vdd vss rx_dv rxd7 rxd6 rxd5 cord_vdd vss rxd4 rxd3 rxd2 io_vdd vss rxd1 rxd0 rx_clk io_vdd vss tx_clk tx_er tx_en cord_vdd vss txd7 txd6 txd5 txd4 io_vdd vss txd3 txd2 cord_vdd vss txd1 txd0 io_vdd vss gtx_clk mdio mdc vss io_vdd reserver clk_to_mac clk_in clk_out mac_clk_en_strap mdix_en_strap io_vdd vss cord_vdd vss multi_en_strap phyaddr4_strap afe_vdd vss pgm_vdd vss cord_vdd bg_vdd bg_ref rx_vdd vss rx_vdd vss vss mdia_p mdia_n vss rx_vdd vss vss mdib_p mdib_n vss rx_vdd vss vss mdic_p mdic_n vss rx_vdd vss vss mdid_p mdid_n vss r4 4.7k c19 0.1uf c14 0.1uf r42 4.7k c34 0.1uf c51 0.1uf r30 49.9 c54 0.1uf c61 0.1uf r11 1k r22 49.9 c52 0.1uf c39 0.1uf c10 0.01uf/2kv c11 0.1uf c46 0.1uf c38 0.1uf r20 0 r6 4.7k r36 9.76k r25 10 r14 1k c48 0.1uf r1 4.7k c53 0.1uf c15 1000pf c57 0.1uf r8 4.7k c22 0.1uf c37 0.1uf r15 1k d3 led r18 49.9 r39 22 r32 10 c36 0.1uf c32 0.1uf d4 led c1 0.1uf c49 0.1uf r19 4.7k r17 49.9 + c43 100uf/16v + c24 100uf/16v r26 75 r9 4.7k c20 1000pf c50 0.1uf c6 0.1uf c9 0.1uf r23 49.9 r5 4.7k r31 75 c31 0.1uf + c16 22uf c8 0.1uf r38 0 c2 0.1uf c21 0.1uf c4 0.1uf r24 75 l3 f.b. r28 10 c12 0.1uf c45 1000pf + c23 100uf/16v r37 4.7k r13 2k c17 0.1uf c13 0.1uf r41 1.5k gtx_clk txd[0..7] tx_en mdio mdc phy_rst# 25mhz vdd25 vdd18 gnd crs col rx_clk rx_dv rxd[0..7] tx_clk option activity led link 10 led link 100 led link 1000 led duplex led phy id : 00110 option
asix electronics corporation 32 ax886 55 p 5 - port 10/100/1000base - t ethernet switch gphy1.sch 1.0 ax88655 p 5-port 10/100/1000base-t ethernet switch --- port 1 g'phy ckt. c 3 10 thursday, march 14, 2002 asix electronics corporation title size document number rev date: sheet of vdd_o gnd vdd_c gnd gnd vdd_o tx_en gnd vdd_o gnd vdd_c phyadd2 speed duplex phyadd1 gnd vdd_o speed1 vdd_o gnd an_en gnd gnd vdd_c vdd_o gnd vdd_c vdd_c gnd gnd phyadd3 phyadd0 rx_vdd25 gnd vdd_o phyadd4 gnd gnd vdd_c vdd_c gnd rx_vdd25 vdd_o gnd gnd vdd_o gnd vdd_o gnd gnd vdd_c gnd txd1 vdd_c txd3 gnd gnd txd5 vdd_o txd2 txd4 txd0 vdd_o gnd txd6 txd7 gnd mdia_p gnd mdid_p gnd gnd gnd gnd vdd_c mdid_n vdd_c gnd gnd vdd_c mdic_p vdd_c mdib_p gnd gnd gnd mdic_n vdd_c mdib_n mdia_n gnd gnd gnd 25m_in gtx_clk vdd_o mdio vdd_o vdd_c gtx_clk tx_en mdio mdc reset# 25m_in vdd25 vdd18 txd[0..7] crs col rx_clk rx_dv tx_clk rxd[0..7] mdid_p mdid_n mdic_n mdic_p mdia_n mdia_p mdib_n mdib_p phyadd2 phyadd3 duplex phyadd0 phyadd1 phyadd4 an_en speed1 speed speed1 speed phyadd0 an_en duplex gnd rxd[0..7] rxd1 rxd5 rxd4 rxd3 rxd6 rxd7 rxd2 rxd0 txd[0..7] col crs tx_clk rx_clk gnd rx_vdd25 vdd25 vdd18 gnd reset# mdc gnd gnd gnd vdd_o rx_vdd25 gnd vdd_c mdi_d+ mdi_c- mdi_c+ mdi_a+ mdi_a- mdi_b- mdi_b+ mdi_d- mdi_a- mdi_b+ mdi_d- mdi_b- mdi_d+ mdi_c- mdi_c+ mdi_a+ gnd rx_dv vdd_o rx_vdd25 rx_vdd25 vdd_o vdd_o rx_vdd25 vdd_o vdd_o vdd_o r83 1.5k c101 0.1uf r71 49.9 c105 0.1uf d7 led c117 0.1uf r45 4.7k c66 0.1uf c87 1000pf r49 4.7k d10 led c102 0.1uf c120 0.1uf r77 49.9 l5 f.b. r82 1.5k r69 75 c96 0.1uf shield jack2 rj45_a 2 4 6 1 3 5 7 8 11 12 c108 1000pf c94 0.1uf c62 0.1uf r54 1k c119 0.1uf c88 0.1uf c116 0.1uf r76 49.9 c121 0.1uf + c103 100uf/16v c91 0.1uf + c79 100uf/16v d6 led c89 1000pf c64 0.1uf r75 4.7k c90 0.1uf r44 4.7k tf2 24hst1041 24 23 22 21 20 19 18 17 16 15 14 13 1 2 3 4 5 6 7 8 9 10 11 12 mct1 mx1+ mx1- mct2 mx2+ mx2- mct3 mx3+ mx3- mct4 mx4+ mx4- tct1 td1+ td1- tct2 td2+ td2- tct3 td3+ td3- tct4 td4+ td4- r63 10 c75 0.1uf c80 0.1uf c86 0.1uf r58 1k c95 0.1uf c112 0.1uf u2 dp83865avh 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 non_ieee_strap reserved /interrupt io_vdd vss tx_tclk activity_led /speed_strap link10_led /speed1_strap link100_led /duplex_strap an_en_strap /link1000_led core_vdd vss phyaddr0_strap /duplex_led phyaddr1_strap io_vdd vss phyaddr2_strap phyaddr3_strap core_vdd vss io_vdd vss reserved tck core_vdd vss tms tdo io_vdd vss tdi /trst /reset vdd_sel_strap core_vdd vss io_vdd vss col crs rx_er io_vdd vss rx_dv rxd7 rxd6 rxd5 cord_vdd vss rxd4 rxd3 rxd2 io_vdd vss rxd1 rxd0 rx_clk io_vdd vss tx_clk tx_er tx_en cord_vdd vss txd7 txd6 txd5 txd4 io_vdd vss txd3 txd2 cord_vdd vss txd1 txd0 io_vdd vss gtx_clk mdio mdc vss io_vdd reserver clk_to_mac clk_in clk_out mac_clk_en_strap mdix_en_strap io_vdd vss cord_vdd vss multi_en_strap phyaddr4_strap afe_vdd vss pgm_vdd vss cord_vdd bg_vdd bg_ref rx_vdd vss rx_vdd vss vss mdia_p mdia_n vss rx_vdd vss vss mdib_p mdib_n vss rx_vdd vss vss mdic_p mdic_n vss rx_vdd vss vss mdid_p mdid_n vss r46 4.7k r64 49.9 r53 1k r72 49.9 r84 4.7k c100 0.1uf c115 0.1uf c72 0.1uf c122 0.1uf c99 0.1uf r48 4.7k c113 0.1uf c71 0.01uf/2kv r56 1k r67 10 c109 0.1uf c107 0.1uf c114 0.1uf c76 1000pf r78 9.76k c118 0.1uf c83 0.1uf r43 4.7k r57 1k c98 0.1uf r81 22 l4 f.b. r50 4.7k r74 10 d9 led c68 0.1uf d8 led r60 49.9 r59 49.9 + c104 100uf/16v c93 0.1uf c97 0.1uf r61 4.7k + c85 100uf/16v c81 1000pf c110 0.1uf c111 0.1uf c70 0.1uf r51 4.7k r68 75 c92 0.1uf r62 0 c67 0.1uf + c77 22uf r47 4.7k r65 49.9 r73 75 r52 4.7k c69 0.1uf c63 0.1uf r80 0 + c84 100uf/16v c82 0.1uf r66 75 l6 f.b. c106 1000pf c65 0.1uf c74 0.1uf c73 0.1uf r55 2k r79 4.7k c78 0.1uf r70 10 gtx_clk txd[0..7] tx_en mdio mdc phy_rst# 25mhz vdd25 vdd18 gnd rx_dv crs tx_clk rx_clk rxd[0..7] col option activity led link 10 led link 100 led link 1000 led duplex led phy id : 01000 option
asix electronics corporation 33 ax886 55 p 5 - port 10/100/1000base - t ethernet switch gphy2.sch 1.0 ax88655 p 5-port 10/100/1000base-t ethernet switch --- port 2 g'phy ckt. c 4 10 thursday, march 14, 2002 asix electronics corporation title size document number rev date: sheet of vdd_o gnd vdd_c gnd gnd vdd_o tx_en gnd vdd_o gnd vdd_c phyadd2 speed duplex phyadd1 gnd vdd_o speed1 vdd_o gnd an_en gnd gnd vdd_c vdd_o gnd vdd_c vdd_c gnd gnd phyadd3 phyadd0 rx_vdd25 gnd vdd_o phyadd4 gnd gnd vdd_c vdd_c gnd rx_vdd25 vdd_o gnd gnd vdd_o gnd vdd_o gnd gnd vdd_c gnd txd1 vdd_c txd3 gnd gnd txd5 vdd_o txd2 txd4 txd0 vdd_o gnd txd6 txd7 gnd mdia_p gnd mdid_p gnd gnd gnd gnd vdd_c mdid_n vdd_c gnd gnd vdd_c mdic_p vdd_c mdib_p gnd gnd gnd mdic_n vdd_c mdib_n mdia_n gnd gnd gnd 25m_in reset# gtx_clk vdd_o mdio vdd_o vdd_c gtx_clk tx_en mdio mdc reset# 25m_in vdd25 vdd18 gnd txd[0..7] crs col rx_clk rx_dv tx_clk rxd[0..7] mdid_p mdid_n rx_vdd25 mdic_n mdic_p rx_vdd25 rx_vdd25 mdia_n mdia_p rx_vdd25 mdib_n mdib_p phyadd2 phyadd3 duplex vdd_o phyadd0 phyadd1 phyadd4 an_en speed1 speed speed1 speed vdd_o phyadd0 an_en duplex vdd_o gnd rxd[0..7] rxd1 rxd5 rxd4 rxd3 rxd6 rxd7 rxd2 rxd0 txd[0..7] col rx_dv tx_clk rx_clk gnd vdd_c rx_vdd25 gnd vdd25 vdd18 vdd_o gnd gnd mdc crs mdi_d+ mdi_c- mdi_c+ mdi_a+ mdi_a- mdi_b- mdi_b+ mdi_d- mdi_a- mdi_b+ mdi_d- mdi_b- mdi_d+ mdi_c- mdi_c+ mdi_a+ gnd gnd vdd_o vdd_o vdd_o d12 led c148 1000pf r113 49.9 c162 0.1uf c166 0.1uf r91 4.7k c178 0.1uf r87 4.7k c127 0.1uf r111 75 c163 0.1uf d15 led c181 0.1uf r119 49.9 c126 0.1uf l8 f.b. r124 1.5k c157 0.1uf shield jack3 rj45_a 2 4 6 1 3 5 7 8 11 12 c169 1000pf r125 1.5k c155 0.1uf c180 0.1uf c149 0.1uf + c164 100uf/16v r96 1k d11 led c177 0.1uf r118 49.9 c182 0.1uf c125 0.1uf r117 4.7k c152 0.1uf + c140 100uf/16v r86 4.7k tf3 24hst1041 24 23 22 21 20 19 18 17 16 15 14 13 1 2 3 4 5 6 7 8 9 10 11 12 mct1 mx1+ mx1- mct2 mx2+ mx2- mct3 mx3+ mx3- mct4 mx4+ mx4- tct1 td1+ td1- tct2 td2+ td2- tct3 td3+ td3- tct4 td4+ td4- r105 10 c150 1000pf c141 0.1uf c147 0.1uf r100 1k c151 0.1uf c129 0.1uf u3 dp83865avh 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 non_ieee_strap reserved /interrupt io_vdd vss tx_tclk activity_led /speed_strap link10_led /speed1_strap link100_led /duplex_strap an_en_strap /link1000_led core_vdd vss phyaddr0_strap /duplex_led phyaddr1_strap io_vdd vss phyaddr2_strap phyaddr3_strap core_vdd vss io_vdd vss reserved tck core_vdd vss tms tdo io_vdd vss tdi /trst /reset vdd_sel_strap core_vdd vss io_vdd vss col crs rx_er io_vdd vss rx_dv rxd7 rxd6 rxd5 cord_vdd vss rxd4 rxd3 rxd2 io_vdd vss rxd1 rxd0 rx_clk io_vdd vss tx_clk tx_er tx_en cord_vdd vss txd7 txd6 txd5 txd4 io_vdd vss txd3 txd2 cord_vdd vss txd1 txd0 io_vdd vss gtx_clk mdio mdc vss io_vdd reserver clk_to_mac clk_in clk_out mac_clk_en_strap mdix_en_strap io_vdd vss cord_vdd vss multi_en_strap phyaddr4_strap afe_vdd vss pgm_vdd vss cord_vdd bg_vdd bg_ref rx_vdd vss rx_vdd vss vss mdia_p mdia_n vss rx_vdd vss vss mdib_p mdib_n vss rx_vdd vss vss mdic_p mdic_n vss rx_vdd vss vss mdid_p mdid_n vss r88 4.7k c136 0.1uf r126 4.7k c156 0.1uf c173 0.1uf r114 49.9 c176 0.1uf c183 0.1uf r106 49.9 r95 1k r90 4.7k c174 0.1uf c132 0.01uf/2kv c161 0.1uf r109 10 c170 0.1uf c168 0.1uf c160 0.1uf r104 0 r120 9.76k c179 0.1uf r98 1k r99 1k c159 0.1uf c175 0.1uf c137 1000pf r92 4.7k r116 10 c144 0.1uf r85 4.7k r123 22 d13 led r102 49.9 l7 f.b. c154 0.1uf c158 0.1uf d14 led c133 0.1uf c171 0.1uf r103 4.7k r101 49.9 + c165 100uf/16v r93 4.7k r110 75 + c146 100uf/16v c142 1000pf c153 0.1uf c128 0.1uf c172 0.1uf c131 0.1uf + c138 22uf r89 4.7k r107 49.9 r115 75 c124 0.1uf r122 0 c130 0.1uf c123 0.1uf + c145 100uf/16v c143 0.1uf r108 75 l9 f.b. r112 10 c135 0.1uf c134 0.1uf c167 1000pf r97 2k r121 4.7k c139 0.1uf r94 4.7k gtx_clk txd[0..7] tx_en mdio mdc phy_rst# 25mhz vdd25 vdd18 gnd rx_dv crs tx_clk rx_clk rxd[0..7] col option activity led link 10 led link 100 led link 1000 led duplex led phy id : 01001 option
asix electronics corporation 34 ax886 55 p 5 - port 10/100/1000base - t ethernet switch gphy3.sch 1.0 ax88655 p 5-port 10/100/1000base-t ethernet switch --- port 3 g'phy ckt. c 5 10 thursday, march 14, 2002 asix electronics corporation title size document number rev date: sheet of vdd_o gnd rx_dv vdd_c gnd gnd vdd_o tx_en gnd vdd_o gnd vdd_c phyadd2 speed duplex phyadd1 gnd vdd_o speed1 vdd_o gnd an_en gnd gnd vdd_c vdd_o gnd vdd_c vdd_c gnd gnd phyadd3 phyadd0 rx_vdd25 gnd vdd_o phyadd4 gnd gnd vdd_c vdd_c gnd rx_vdd25 vdd_o gnd gnd vdd_o gnd vdd_o gnd gnd vdd_c gnd txd1 vdd_c txd3 gnd gnd txd5 vdd_o txd2 txd4 txd0 vdd_o gnd txd6 txd7 gnd mdia_p gnd mdid_p gnd gnd gnd gnd vdd_c mdid_n vdd_c gnd gnd vdd_c mdic_p vdd_c mdib_p gnd gnd gnd mdic_n vdd_c mdib_n mdia_n gnd gnd gnd gtx_clk vdd_o mdio vdd_o vdd_c gtx_clk tx_en mdio mdc reset# 25m_in vdd25 vdd18 txd[0..7] crs col rx_clk rx_dv tx_clk rxd[0..7] mdid_p mdid_n rx_vdd25 mdic_n mdic_p rx_vdd25 rx_vdd25 mdia_n mdia_p rx_vdd25 mdib_n mdib_p phyadd2 phyadd3 duplex vdd_o phyadd0 phyadd1 phyadd4 an_en speed1 speed speed1 speed phyadd0 an_en duplex vdd_o vdd_o gnd rxd[0..7] rxd1 rxd5 rxd4 rxd3 rxd6 rxd7 rxd2 rxd0 txd[0..7] tx_clk rx_clk gnd reset# vdd_c rx_vdd25 gnd vdd25 vdd18 vdd_o mdc col crs 25m_in mdi_d+ mdi_c- mdi_c+ mdi_a+ mdi_a- mdi_b- mdi_b+ mdi_d- mdi_a- mdi_b+ mdi_d- mdi_b- mdi_d+ mdi_c- mdi_c+ mdi_a+ gnd vdd_o gnd gnd gnd gnd vdd_o vdd_o d17 led r155 49.9 c223 0.1uf c227 0.1uf c239 0.1uf r129 4.7k c188 0.1uf c209 1000pf c224 0.1uf d20 led c242 0.1uf r133 4.7k l11 f.b. r146 0 r166 1.5k r153 75 c230 1000pf c216 0.1uf r161 49.9 c184 0.1uf c241 0.1uf c210 0.1uf c218 0.1uf shield jack4 rj45_a 2 4 6 1 3 5 7 8 11 12 c243 0.1uf + c225 100uf/16v r138 1k r160 49.9 + c201 100uf/16v d16 led c238 0.1uf c211 1000pf c186 0.1uf r159 4.7k c213 0.1uf r128 4.7k tf4 24hst1041 24 23 22 21 20 19 18 17 16 15 14 13 1 2 3 4 5 6 7 8 9 10 11 12 mct1 mx1+ mx1- mct2 mx2+ mx2- mct3 mx3+ mx3- mct4 mx4+ mx4- tct1 td1+ td1- tct2 td2+ td2- tct3 td3+ td3- tct4 td4+ td4- r147 10 c208 0.1uf r142 1k c194 0.1uf c212 0.1uf u4 dp83865avh 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 non_ieee_strap reserved /interrupt io_vdd vss tx_tclk activity_led /speed_strap link10_led /speed1_strap link100_led /duplex_strap an_en_strap /link1000_led core_vdd vss phyaddr0_strap /duplex_led phyaddr1_strap io_vdd vss phyaddr2_strap phyaddr3_strap core_vdd vss io_vdd vss reserved tck core_vdd vss tms tdo io_vdd vss tdi /trst /reset vdd_sel_strap core_vdd vss io_vdd vss col crs rx_er io_vdd vss rx_dv rxd7 rxd6 rxd5 cord_vdd vss rxd4 rxd3 rxd2 io_vdd vss rxd1 rxd0 rx_clk io_vdd vss tx_clk tx_er tx_en cord_vdd vss txd7 txd6 txd5 txd4 io_vdd vss txd3 txd2 cord_vdd vss txd1 txd0 io_vdd vss gtx_clk mdio mdc vss io_vdd reserver clk_to_mac clk_in clk_out mac_clk_en_strap mdix_en_strap io_vdd vss cord_vdd vss multi_en_strap phyaddr4_strap afe_vdd vss pgm_vdd vss cord_vdd bg_vdd bg_ref rx_vdd vss rx_vdd vss vss mdia_p mdia_n vss rx_vdd vss vss mdib_p mdib_n vss rx_vdd vss vss mdic_p mdic_n vss rx_vdd vss vss mdid_p mdid_n vss r130 4.7k c197 0.1uf c202 0.1uf r156 49.9 r168 4.7k c217 0.1uf c234 0.1uf c237 0.1uf c244 0.1uf r148 49.9 r137 1k r132 4.7k c235 0.1uf c193 0.01uf/2kv c222 0.1uf r151 10 c231 0.1uf c229 0.1uf c221 0.1uf c198 1000pf r162 9.76k c240 0.1uf r140 1k r141 1k c220 0.1uf c236 0.1uf c190 0.1uf r134 4.7k r158 10 c205 0.1uf r127 4.7k r136 4.7k r144 49.9 l10 f.b. r165 22 c215 0.1uf c219 0.1uf d19 led d18 led c232 0.1uf r145 4.7k r143 49.9 + c226 100uf/16v r135 4.7k r152 75 + c207 100uf/16v c203 1000pf c189 0.1uf c233 0.1uf c192 0.1uf r149 49.9 c187 0.1uf r157 75 c214 0.1uf + c199 22uf r131 4.7k c185 0.1uf r164 0 c204 0.1uf r150 75 l12 f.b. c191 0.1uf c196 0.1uf c195 0.1uf c228 1000pf + c206 100uf/16v r139 2k r163 4.7k c200 0.1uf r154 10 r167 1.5k gtx_clk txd[0..7] tx_en mdio mdc phy_rst# 25mhz vdd25 vdd18 gnd rx_dv crs tx_clk rx_clk rxd[0..7] col option activity led link 10 led link 100 led link 1000 led duplex led phy id : 01010 option
asix electronics corporation 35 ax886 55 p 5 - port 10/100/1000base - t ethernet switch gphy4.sch 1.0 ax88655 p 5-port 10/100/1000base-t ethernet switch --- port 4 g'phy ckt. c 6 10 thursday, march 14, 2002 asix electronics corporation title size document number rev date: sheet of vdd_o gnd vdd_c gnd gnd vdd_o tx_en gnd vdd_o gnd vdd_c phyadd2 speed duplex phyadd1 gnd vdd_o speed1 vdd_o gnd an_en gnd gnd vdd_c vdd_o gnd vdd_c vdd_c gnd gnd phyadd3 phyadd0 rx_vdd25 gnd vdd_o phyadd4 gnd gnd vdd_c vdd_c gnd rx_vdd25 vdd_o gnd gnd vdd_o gnd vdd_o gnd gnd vdd_c gnd txd1 vdd_c txd3 gnd gnd txd5 vdd_o txd2 txd4 txd0 vdd_o gnd txd6 txd7 gnd mdia_p gnd mdid_p gnd gnd gnd gnd vdd_c mdid_n vdd_c gnd gnd vdd_c mdic_p vdd_c mdib_p gnd gnd gnd mdic_n vdd_c mdib_n mdia_n gnd gnd gnd 25m_in gtx_clk vdd_o vdd_o vdd_c gtx_clk tx_en mdio mdc reset# 25m_in vdd25 vdd18 gnd txd[0..7] crs col rx_clk rx_dv tx_clk rxd[0..7] mdid_p mdid_n rx_vdd25 mdic_n mdic_p rx_vdd25 rx_vdd25 mdia_n mdia_p rx_vdd25 mdib_n mdib_p phyadd2 phyadd3 duplex vdd_o phyadd0 phyadd1 phyadd4 an_en speed1 speed speed1 speed vdd_o phyadd0 an_en duplex vdd_o gnd rxd[0..7] rxd1 rxd5 rxd4 rxd3 rxd6 rxd7 rxd2 rxd0 txd[0..7] crs tx_clk rx_clk gnd vdd_c rx_vdd25 gnd vdd25 vdd18 gnd vdd_o gnd gnd reset# mdio mdc col mdi_d+ mdi_c- mdi_c+ mdi_a+ mdi_a- mdi_b- mdi_b+ mdi_d- mdi_a- mdi_b+ mdi_d- mdi_b- mdi_d+ mdi_c- mdi_c+ mdi_a+ gnd rx_dv vdd_o vdd_o vdd_o c288 0.1uf c276 0.1uf r197 49.9 c305 0.1uf c271 0.1uf d21 led c304 0.1uf c284 0.1uf c285 0.1uf c281 0.1uf u5 dp83865avh 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 non_ieee_strap reserved /interrupt io_vdd vss tx_tclk activity_led /speed_strap link10_led /speed1_strap link100_led /duplex_strap an_en_strap /link1000_led core_vdd vss phyaddr0_strap /duplex_led phyaddr1_strap io_vdd vss phyaddr2_strap phyaddr3_strap core_vdd vss io_vdd vss reserved tck core_vdd vss tms tdo io_vdd vss tdi /trst /reset vdd_sel_strap core_vdd vss io_vdd vss col crs rx_er io_vdd vss rx_dv rxd7 rxd6 rxd5 cord_vdd vss rxd4 rxd3 rxd2 io_vdd vss rxd1 rxd0 rx_clk io_vdd vss tx_clk tx_er tx_en cord_vdd vss txd7 txd6 txd5 txd4 io_vdd vss txd3 txd2 cord_vdd vss txd1 txd0 io_vdd vss gtx_clk mdio mdc vss io_vdd reserver clk_to_mac clk_in clk_out mac_clk_en_strap mdix_en_strap io_vdd vss cord_vdd vss multi_en_strap phyaddr4_strap afe_vdd vss pgm_vdd vss cord_vdd bg_vdd bg_ref rx_vdd vss rx_vdd vss vss mdia_p mdia_n vss rx_vdd vss vss mdib_p mdib_n vss rx_vdd vss vss mdic_p mdic_n vss rx_vdd vss vss mdid_p mdid_n vss c300 0.1uf c302 0.1uf r174 4.7k r206 0 r184 1k c266 0.1uf r202 49.9 + c260 22uf c279 0.1uf c283 0.1uf r205 4.7k c248 0.1uf c254 0.01uf/2kv + c286 100uf/16v c269 0.1uf + c268 100uf/16v c273 0.1uf c261 0.1uf d23 led r175 4.7k r182 1k r208 1.5k c293 0.1uf c299 0.1uf r189 10 c270 1000pf + c287 100uf/16v c258 0.1uf r171 4.7k + c262 100uf/16v r185 49.9 r179 1k r194 75 c274 0.1uf r203 49.9 c251 0.1uf r199 75 r180 1k c275 0.1uf l14 f.b. c247 0.1uf c256 0.1uf c250 0.1uf c301 0.1uf r193 10 c265 0.1uf c278 0.1uf c246 0.1uf r183 1k c290 0.1uf c296 0.1uf r200 10 r170 4.7k c272 1000pf r172 4.7k c249 0.1uf c280 0.1uf c282 0.1uf c295 0.1uf r181 2k d24 led shield jack5 rj45_a 2 4 6 1 3 5 7 8 11 12 c297 0.1uf r210 4.7k r209 1.5k r195 75 d25 led c277 0.1uf c263 0.1uf r207 22 r201 4.7k c255 0.1uf r188 0 r191 49.9 tf5 24hst1041 24 23 22 21 20 19 18 17 16 15 14 13 1 2 3 4 5 6 7 8 9 10 11 12 mct1 mx1+ mx1- mct2 mx2+ mx2- mct3 mx3+ mx3- mct4 mx4+ mx4- tct1 td1+ td1- tct2 td2+ td2- tct3 td3+ td3- tct4 td4+ td4- c303 0.1uf r177 4.7k c259 1000pf c252 0.1uf c257 0.1uf r176 4.7k c292 0.1uf r187 4.7k r190 49.9 c298 0.1uf c253 0.1uf c289 1000pf + c267 100uf/16v c291 1000pf r173 4.7k d22 led r198 49.9 l15 f.b. r192 75 r169 4.7k c245 0.1uf c264 1000pf r186 49.9 r204 9.76k l13 f.b. c294 0.1uf r196 10 r178 4.7k gtx_clk txd[0..7] tx_en mdio mdc phy_rst# 25mhz vdd25 vdd18 gnd rx_dv crs tx_clk rx_clk rxd[0..7] col option activity led link 10 led link 100 led link 1000 led duplex led phy id : 01011 option
asix electronics corporation 36 ax886 55 p 5 - port 10/100/1000base - t ethernet switch gsw_ckt.sch 1.0 ax88655 p 5-port 10/100/1000base-t ethernet switch --- ax88655 p ckt. c 7 10 thursday, march 14, 2002 asix electronics corporation title size document number rev date: sheet of gnd rxd33 rxd22 txd03 gtx_clk0 rx_clk1 col3 gnd tx_en3 rx_clk2 col2 rxd30 rx_dv2 gtx_clk2 rxd37 txd02 gclk_en# gtx_clk0 2.5v tx_clk3 txd27 rx_dv0 gnd txd46 tx_clk4 2.5v txd15 txd13 col4 2.5v rxd16 gnd rxd3[0..7] txd43 tx_clk2 rx_dv2 txd12 gnd gnd txd23 txd06 gtx_clk4 rx_clk0 vdd33 tx_en0 rx_clk0 rxd36 rxd41 txd26 txd01 2.5v txd40 rxd40 gnd txd4[0..7] rxd12 tx_en4 vdd25 crs1 col0 2.5v rxd17 txd4[0..7] rxd2[0..7] gnd rxd45 2.5v col4 rxd34 filter 2.5v gnd rxd46 gtx_clk3 gtx_clk1 rxd00 2.5v rx_clk1 crs1 gtx_clk2 rxd4[0..7] txd2[0..7] rxd43 tx_clk0 rxd2[0..7] 2.5v col0 rx_dv3 rxd44 txd44 rx_dv4 tx_en0 tx_en1 rxd35 rxd42 gnd 2.5v col1 txd22 rxd47 gnd gnd crs4 rxd02 txd45 gnd col1 rxd11 filter 2.5va reset# gnd gclk_en# txd05 mdc gnd crs2 rxd10 gnd txd36 rxd31 txd35 txd37 2.5v crs3 2.5va tx_clk1 crs4 3.3v rxd14 x_in rx_dv3 sysclk rx_clk3 gnd gnd crs2 rxd1[0..7] txd3[0..7] 2.5v rx_clk4 gnd txd47 gnd sysclk_en# rx_clk4 2.5v txd31 txd24 txd0[0..7] 2.5v rxd23 txd16 txd34 gtx_clk3 gnd gnd gtx_clk4 txd00 gnd sdc gclk txd07 vdd25 rxd0[0..7] 2.5v txd04 sdio tx_en2 vdd33 txd2[0..7] rxd26 sdc tx_clk3 txd3[0..7] txd42 tx_en4 gnd rxd25 rxd15 txd25 col3 2.5va 2.5v rxd4[0..7] rxd20 vdd25 crs3 sdio tx_clk0 gnd rxd24 rxd03 txd0[0..7] x_in rxd13 tx_clk2 rxd01 gnd tx_clk1 rxd1[0..7] rxd21 rxd3[0..7] txd14 rxd04 3.3v tx_en3 tx_en2 x_out 3.3v crs0 reset# rxd32 tx_en1 txd11 rxd05 txd20 txd21 rx_dv0 2.5v mdio gnd txd30 gclk sysclk rx_dv1 rxd27 rxd06 tx_clk4 x_out txd32 txd1[0..7] txd41 rx_clk2 gnd crs0 rx_dv1 txd17 gnd gnd txd10 2.5v rxd07 gtx_clk1 gnd txd33 txd1[0..7] col2 rx_dv4 rxd0[0..7] rx_clk3 sysclk_en# 2.5v mdio mdc 2.5v r215 1.5k r216 1.5k c338 1000pf c339 0.1uf c315 1000pf r234 47 + c310 220uf/16v c327 0.1uf r211 0 l18 f.b. r220 47 l17 f.b. + c336 100uf/16v c348 0.1uf r221 47 l16 f.b. c325 0.1uf c329 0.1uf c312 0.1uf c330 0.1uf r219 0 r232 0 r223 0 c328 0.1uf c346 1000pf + c334 100uf/16v r214 0 c341 0.1uf c340 1000pf c331 0.1uf c332 0.1uf + c311 220uf/16v + c333 100uf/16v r224 0 r226 47 r213 47 c318 0.1uf c344 1000pf r231 47 r230 47 r227 0 c323 0.1uf c322 0.1uf c319 0.1uf r229 0 c347 0.1uf r233 0 r217 10k c321 0.1uf c316 0.1uf r212 47 r235 47 c326 0.1uf c313 1000pf c337 0.1uf c345 0.1uf r236 0 l19 f.b. c309 20pf c308 20pf y1 27mhz c317 0.1uf c320 0.1uf c343 0.1uf r228 1m r222 680 + c335 100uf/16v c306 39pf r218 10k c307 680pf r225 47 l20 f.b. u6 ax88655 p 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 24 25 26 27 28 29 30 31 32 22 23 33 34 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 35 36 37 38 39 41 42 40 158 159 43 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 209 210 211 212 213 214 215 216 217 218 219 220 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 241 242 243 244 245 246 247 248 249 250 251 252 253 254 255 256 txd0[4] txd0[5] txd0[6] txd0[7] tx_en0 vss vdd25 nc nc vss vss vss vss nc nc nc nc vss vss vss nc nc nc nc nc nc nc nc nc nc vdd25 nc vss vdd33 crs1 col1 rxd1[0] rxd1[1] rxd1[2] rxd1[3] rxd1[4] rxd1[5] rxd1[6] rxd1[7] rx_clk1 rx_dv1 vss gtx_clk1 vdd25 tx_clk1 txd1[0] txd1[1] txd1[2] txd1[3] txd1[4] txd1[5] txd1[6] txd1[7] tx_en1 vss vdd25 crs2 col2 rxd2[0] rxd2[1] rxd2[2] rxd2[3] rxd2[4] rxd2[5] rxd2[6] rxd2[7] rx_clk2 rx_dv2 vss gtx_clk2 vdd25 tx_clk2 txd2[0] txd2[1] txd2[2] txd2[3] txd2[4] txd2[5] txd2[6] txd2[7] tx_en2 vss vdd25 crs3 col3 rxd3[0] rxd3[1] rxd3[2] rxd3[3] rxd3[4] rxd3[5] rxd3[6] rxd3[7] rx_clk3 rx_dv3 vss gtx_clk3 vdd25 tx_clk3 txd3[0] txd3[1] txd3[2] txd3[3] txd3[4] txd3[5] txd3[6] txd3[7] tx_en3 vss vdd25 crs4 col4 rxd4[0] rxd4[1] rxd4[2] rxd4[3] rxd4[4] rxd4[5] rxd4[6] rxd4[7] rx_clk4 rx_dv4 vss g_txclk4 vdd25 tx_clk4 txd4[0] txd4[1] txd4[2] txd4[3] txd4[4] txd4[5] txd4[6] txd4[7] tx_en4 vss vdd25 sid0 sid1 sid2 sid3 sid4 /gclk_en x_in x_out avbb25 avdd25a avss25a avss25d avdd25d filter /sysclk_en vss nc vss gclk vdd25 sdio sdc mdio mdc nc sysclk vss /rst vdd33 nc nc nc nc gpio0 gpio1 gpio2 gpio3 gpio4 vss vdd25 nc nc vss vss vss vss nc nc nc nc vss vss vss nc vdd25 nc nc nc nc nc nc nc nc nc nc vss vdd25 nc nc vss vss vss vss nc nc nc nc vss vss vss nc vdd25 nc nc nc nc nc nc nc nc nc nc vss vdd25 crs0 col0 rxd0[0] rxd0[1] rxd0[2] rxd0[3] rxd0[4] rxd0[5] rxd0[6] rxd0[7] rx_clk0 rx_dv0 vss gtx_clk0 vdd25 tx_clk0 txd0[0] txd0[1] txd0[2] txd0[3] c314 0.1uf c324 0.1uf c342 0.1uf rx_clk2 sdio rx_rv4 crs4 crs0 gclk rx_dv0 sysclk tx_clk4 col0 gnd rx_clk4 vdd25_2 rxd2[0..7] rx_rv2 col1 sdc reset# rx_clk0 tx_clk0 rx_dv1 crs1 rx_clk1 col2 mdio col4 crs3 rx_clk3 crs2 rxd1[0..7] rx_rv3 tx_clk1 rxd4[0..7] rxd3[0..7] mdc tx_clk2 col3 vdd33 tx_clk3 rxd0[0..7] gtx_clk0 txd0[0..7] tx_en0 txd1[0..7] gtx_clk1 tx_en1 txd2[0..7] gtx_clk2 tx_en2 txd3[0..7] gtx_clk3 tx_en3 txd4[0..7] gtx_clk4 tx_en4 if sysclk_en pull down, the sysclk input 90mhz, else the x_in & x_out input 27mhz.
asix electronics corporation 37 ax886 55 p 5 - port 10/100/1000base - t ethernet switch osc_ckt.sch 1.0 ax88655 p 5-port 10/100/1000base-t ethernet switch --- osc ckt. b 8 10 thursday, march 14, 2002 asix electronics corporation title size document number rev date: sheet of vdd33 sysclk vdd33 gnd gnd clk_vdd1 25mhz 25m_p1 25m_p4 25m_p0 25m_p1 25m_p2 25m_p4 25m_p3 gclk sysclk vdd33 clk_vdd1 vdd33 gnd gclk 25m_p0 25mhz vdd33 25m_p3 25m_p2 c353 0.1uf l22 f.b. u8 pll102_05 1 2 3 4 5 6 7 8 ref clk2 clk1 gnd clk3 vdd clk4 clkout c354 0.1uf r242 10 r240 10 r238 10 r243 10 r241 10 r239 10 r244 10 c351 0.1uf l23 f.b. c352 0.1uf u9 90mhz 8 4 5 vcc gnd out r237 10 l21 f.b. u7 125mhz 8 4 5 vcc gnd out l24 f.b. c356 0.1uf c350 0.1uf c355 0.1uf u10 25mhz 8 4 5 vcc gnd out r245 10 c349 0.1uf vdd33 gnd sysclk gclk 25m_p0 25m_p1 25m_p2 25m_p3 25m_p4
asix electronics corporation 38 ax886 55 p 5 - port 10/100/1000base - t ethernet switch power_ckt.sch 1.0 ax88655 p 5-port 10/100/1000base-t ethernet switch --- power input ckt. c 9 10 thursday, march 14, 2002 asix electronics corporation title size document number rev date: sheet of 5v vdd33 vdd18_2 5vsb vdd18_1 vdd33 vdd33 vdd33 vdd33 vdd33 vdd33 vdd25 vdd33 vdd33 gnd vdd33 rst#_sw vdd33 rst#_p0 vdd33 vdd25 vdd18_1 rst_ctl# rst#_p12 rst#_p0 rst#_sw rst_ctl# vdd33 vdd18_2 3.3v 3.3v gnd 5v gnd 5v gnd 12v 3.3v gnd ps_on 5v gnd gnd 5v gnd 5vsb vdd18_1 3.3v 3.3v 3.3v gnd vdd25 vdd33 vdd33 vdd18_2 vdd25_2 5v vdd25_2 gnd gnd gnd gnd gnd gnd gnd gnd 5v 5v vdd25 rst#_p34 rst#_p12 rst#_p34 u16a 74hc123 14 15 1 2 3 13 4 cext rext/cext a b clr q q r269 0 r264 10k c407 1000pf c390 0.1uf c375 0.1uf r252 301 c387 1000pf r254 1k c386 0.1uf d29 led tp9 test point 1 d27 led + c384 220uf/16v c374 1000pf c391 1000pf c409 1000pf u14 lt1085 3 4 2 1 vin tab/out vout adj/gnd c419 0.1uf c361 0.1uf c408 0.1uf c362 1000pf tp7 test point 1 + c385 220uf/16v r250 1k r255 1k c421 0.1uf c420 0.1uf c418 0.1uf + c412 220uf/16v c414 0.1uf c373 0.1uf c372 1000pf r246 680 tp1 test point 1 u11 lt1085 3 4 2 1 vin tab/out vout adj/gnd + c357 220uf/16v + c358 220uf/16v r248 301 tp13 test point 1 tp14 test point 1 c363 0.1uf c415 0.1uf c359 0.1uf tp3 test point 1 c416 1000pf c370 0.1uf r249 100 c364 1000pf + c377 220uf/16v + c376 220uf/16v c382 0.1uf r261 4.7k c378 0.1uf + c413 220uf/16v u13 lt1085 3 4 2 1 vin tab/out vout adj/gnd j1 con2 1 2 c397 0.1uf + c365 220uf/16v c424 0.1uf c393 1000pf c394 0.1uf c388 0.1uf c389 1000pf c379 1000pf u17b 74hc04 3 4 c402 0.1uf tp8 test point 1 u17c 74hc04 5 6 c395 1000pf u17d 74hc04 9 8 d28 1n5402 c417 0.1uf r259 100k tp11 test point 1 + c371 220uf/16v u17e 74hc04 11 10 c369 0.1uf tp12 test point 1 r257 1k c368 1000pf c396 0.1uf c401 1000pf c367 0.1uf c360 1000pf + c392 220uf/16v c400 0.1uf u19 xc61f 3 1 2 vin vout vss c366 1000pf d26 1n5402 c399 1000pf tp10 test point 1 + c398 220uf/16v r268 10k r265 0 c383 1000pf r251 680 tp5 test point 1 + c423 4.7uf/16v tp6 test point 1 r260 10k tp2 test point 1 u12 atx power 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 3.3v 3.3v gnd 5v gnd 5v gnd pw_ok 5vsb 12v 3.3v -12v gnd ps-on gnd gnd gnd -5v 5v 5v + c403 220uf/16v c405 0.1uf r258 1k + c404 220uf/16v tp4 test point 1 c411 1000pf c380 0.1uf u18a 74hc00 1 2 3 14 7 c410 0.1uf u15 lt1085 3 4 2 1 vin tab/out vout adj/gnd c381 1000pf r256 1k c406 1000pf u17a 74hc04 1 2 r247 4.7k r263 0 s2 sw pushbutton c422 0.1uf s1 sw spst r253 100/2w d30 1n4148 vdd33 vdd25 vdd18_1 gnd rst_ctl# vdd18_2 vdd25_2 rst#_p34 rst#_p12 rst#_p0 rst#_sw 5v input gnd 1.8v output gnd gnd 3.3v input 1.8v output gnd 3.3v power led 5v power led gnd gnd 2.5v output 2.5v output gnd option option for external rc reset ic
asix electronics corporation 39 ax886 55 p 5 - port 10/100/1000base - t ethernet switch rom_ckt.sch 1.0 ax88655 p 5-port 10/100/1000base-t ethernet switch ---serial eeprom ckt. b 10 10 thursday, march 14, 2002 asix electronics corporation title size document number rev date: sheet of vdd33 vdd33 pd2 gnd sdio pd0 rst_ctl# rst_ctl# vdd33 gnd sdio sdc busy sdio gnd strob# init# pd2 pd0 rst_ctl# busy vdd33 gnd vdd33 init# vdd33 gnd rst_ctl# vdd33 strob# vdd33 gnd vdd33 sdio rst_ctl# sdc vdd33 sdc r283 100 u20 74hc125 14 3 6 8 11 2 5 9 12 1 4 10 13 vcc 1y 2y 3y 4y 1a 2a 3a 4a 1oe 2oe 3oe 4oe r276 4.7k r275 4.7k r270 4.7k j2 print_port 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 r278 100 r272 4.7k r271 4.7k r277 100 r273 100 r280 100 c425 0.1uf c426 0.1uf r281 0 r274 4.7k u18b 74hc00 4 5 6 14 7 u18c 74hc00 9 10 8 14 7 r279 0 r282 0 u21 at24c16b 1 2 3 4 5 6 7 8 a0 a1 a2 gnd sda scl wp vcc vdd33 gnd sdio sdc rst_ctl# init#(i) busy(o) pd0(i) pd2(i) strob#(i) (seeprom)
asix electronic 40 http://www.asix.com.tw revision date comment v. 1.0 3 /14/02 initial release. 4f, no.8, hsin ann rd., science - based industrial park, hsinchu, taiwan, r.o.c. tel: 886 - 3 - 5799500 fax: 886 - 3 - 5799558 email: support@asix.com.tw web: http://www.asix.com.tw revision history

▲Up To Search▲

Price & Availability of AX88655P

	To Download AX88655P Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .